A New Coarse-Grained Reconfigurable Architecture with Fast Data Relay and Its Compilation Flow
نویسندگان
چکیده
{luwan2, cdong3, dchen}@illinois.edu Enabling Hardware Support for Fast Data Relay Architectural overview: Host CPU initializes the kernel computation on our FDR-CGRA. DMA is in charge of system-level dataflow. FDR-CGRA can focus on accelerating time-consuming kernels. Processing elements: Support concurrent computation and communication with dedicated computing path and bypassing path for Fast Data Relay. Use bypassing register file to temporary deposition of intermediate data from other PEs. Wire-based companion channels: Inter-tile communication: direct connections between PEs on the tile boundaries. Intra-tile communication: using companion channels. • Vertical : send scalar data from the sender PE to any PE in the same column. • Horizontal: send scalar data from the sender PE to any PE in the same row. Fast Data Relay (FDR) FDR is a combination of hardware and compiler techniques to enable efficient multi-cycle data communication among Processing Elements (PEs) in a Coarse-Grained Reconfigurable Architecture (CGRA). We name the proposed architecture FDR-CGRA.
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